1. Field of the Invention
The present invention generally relates to integrated circuit dynamic random access memories (DRAMs) and, more particularly, to trench capacitor and strap construction in DRAMs.
2. Background Description
Formation of a strap for connection of a DRAM transistor to the storage trench has required difficult process steps, regardless of whether the strap is formed on the surface or buried. In addition, a strap can take space in the cell which limits the minimum cell size.
In an effort to save space, selective silicon has been used to form the transistor in space over the trench seeded from the single crystal substrate. In this case a dielectric cap over the trench is needed to prevent heavily doped trench polysilicon from shorting out the transistor. After the transistor has been formed, a contact is made in the dielectric cap to connect the source of the transistor to the trench polysilicon.
This structure has not actually provided space savings as compared with designs that put the trench in a location that would otherwise be used for isolation. In addition, selective silicon has not provided performance comparable to bulk silicon from the viewpoint of transistor leakage, a key parameter for DRAM performance.
Thus, a better solution is needed that saves space while avoiding a reduction in performance, this solution is provided by the present invention.